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Intel386TM EX Embedded Microprocessor
Datasheet
Product Features
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Static Intel386TM CPU Core -- Low Power Consumption -- Operating Power Supply EXTB: 2.7 V to 3.6 V EXTC: 4.5 V to 5.5 V -- Operating Frequency 20 MHz EXTB at 2.7 V to 3.6 V 25 MHz EXTB at 3.0 V to 3.6 V; 25/33 MHz EXTC at 4.5 V to 5.5 V Transparent Power-management System Architecture -- Intel System Management Mode Architecture Extension for Truly Compatible Systems -- Power Management Transparent to Operating Systems and Application Programs -- Programmable Power-management Modes Powerdown Mode -- Clock Stopping at Any Time -- Only 10-20 A Typical CPU Sink Current Full 32-bit Internal Architecture -- 8-, 16-, 32-bit Data Types -- 8 General Purpose 32-bit Registers Runs Intel386 Architecture Software in a Cost-effective 16-bit Hardware Environment -- Runs Same Applications and Operating Systems as the Intel386 SX and Intel386 DX Processors -- Object Code Compatible with 8086, 80186, 80286, and Intel386 Processors High-performance 16-bit Data Bus -- Two-clock Bus Cycles -- Address Pipelining Allows Use of Slower, Inexpensive Memories
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Extended Temperature Range Integrated Memory Management Unit -- Virtual Memory Support -- Optional On-chip Paging -- 4 Levels of Hardware-enforced Protection -- MMU Fully Compatible with MMUs of the 80286 and Intel386 DX Processors Virtual 8086 Mode Allows Execution of 8086 Software in a Protected and Paged System Large Uniform Address Space -- 64 Megabyte Physical -- 64 Terabyte Virtual -- 4 Gigabyte Maximum Segment Size On-chip Debugging Support Including Breakpoint Registers Complete System Development Support High Speed CHMOS Technology Two Package Types -- 132-pin Plastic Quad Flatpack -- 144-pin Thin Quad Flatpack Integrated Peripheral Functions -- Clock and Power Management Unit -- Chip-select Unit -- Interrupt Control Unit -- Timer/Counter Unit -- Watchdog Timer Unit -- Asynchronous Serial I/O Unit -- Synchronous Serial I/O Unit -- Parallel I/O Unit -- DMA and Bus Arbiter Unit -- Refresh Control Unit -- JTAG-compliant Test-logic Unit
This datasheet applies to devices marked EXTB and EXTC. If you require information about devices marked EXSA or EXTA, refer to a previous revision of this datasheet, order number 272420-004.
Order Number: 272420-007 October 1998
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel386TM EX Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.
Datasheet
Intel386TM EX Embedded Microprocessor
Contents
1.0 2.0 3.0 4.0 Introduction .................................................................................................................. 7 Pin Assignment...........................................................................................................8 Pin Description..........................................................................................................12 Functional Description...........................................................................................19
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 Clock Generation and Power Management Unit ................................................. 19 Chip-select Unit ................................................................................................... 19 Interrupt Control Unit ........................................................................................... 19 Timer/Counter Unit .............................................................................................. 20 Watchdog Timer Unit........................................................................................... 20 Asynchronous Serial I/O Unit ..............................................................................20 Synchronous Serial I/O Unit ................................................................................ 21 Parallel I/O Unit ................................................................................................... 21 DMA and Bus Arbiter Unit ................................................................................... 21 Refresh Control Unit............................................................................................22 JTAG Test-logic Unit ........................................................................................... 22
5.0
Design Considerations ..........................................................................................23
5.1 5.2 5.3 Instruction Set ..................................................................................................... 23 Component and Revision Identifiers ................................................................... 24 Package Thermal Specifications .........................................................................24
6.0
Electrical Specifications........................................................................................27
6.1 6.2 6.3 Maximum Ratings................................................................................................ 27 DC Specifications ................................................................................................ 28 AC Specifications ................................................................................................ 30
7.0
Bus Cycle Waveforms ............................................................................................47
Figures
1 2 3 4 5 6 7 8 9 10 Intel386TM EX Embedded Processor Block Diagram ............................................ 7 Intel386TM EX Embedded Processor 132-Pin PQFP Pin Assignment .................. 8 Intel386TM EX Embedded Processor 144-Pin TQFP Pin Assignment................. 10 Maximum Case Temperature vs. Frequency for Typical Power Values (132-lead PQFP, Vcc = 5.5 V) ............................................................................. 25 Maximum Case Temperature vs. Frequency for Typical Power Values (144-lead TQFP, Vcc = 5.5 V nominal) ................................................................ 25 Maximum Case Temperature vs. Frequency for Typical Power Values (132-lead PQFP, Vcc = 3.6 V) ............................................................................. 26 Maximum Case Temperature vs. Frequency for Typical Power Values (144-lead TQFP, Vcc = 3.6 V)..............................................................................26 Drive Levels and Measurement Points for AC Specifications (EXTC) ................ 30 Drive Levels and Measurement Points for AC Specifications (EXTB) ................ 31 AC Test Loads..................................................................................................... 42
Datasheet
3
Intel386TM EX Embedded Microprocessor
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CLK2 Waveform .................................................................................................. 42 AC Timing Waveforms -- Input Setup and Hold Timing ..................................... 43 AC Timing Waveforms -- Output Valid Delay Timing ......................................... 44 AC Timing Waveforms -- Output Valid Delay Timing for External Late READY#........................................................................................ 44 AC Timing Waveforms -- Output Float Delay and HLDA Valid Delay Timing .... 45 AC Timing Waveforms -- RESET Setup and Hold Timing and Internal Phase .. 45 AC Timing Waveforms -- Relative Signal Timing ............................................... 46 AC Timing Waveforms -- SSIO Timing .............................................................. 46 AC Timing Waveforms -- Timer/Counter Timing ................................................ 46 Basic Internal and External Bus Cycles .............................................................. 47 Nonpipelined Address Read Cycles.................................................................... 48 Pipelined Address Cycle ..................................................................................... 49 16-bit Cycles to 8-bit Devices (using BS8#) ........................................................ 50 Basic External Bus Cycles .................................................................................. 51 Nonpipelined Address Write Cycles .................................................................... 52 Halt Cycle ............................................................................................................ 53 Basic Refresh Cycle ............................................................................................ 54 Refresh Cycle During HOLD/HLDA .................................................................... 55 LOCK# Signal During Address Pipelining ........................................................... 56 Interrupt Acknowledge Cycles............................................................................. 56
Tables
1 2 3 4 5 6 7 8 9 10 11 12 132-Pin PQFP Pin Assignment ............................................................................. 9 144-Pin TQFP Pin Assignment ........................................................................... 11 Pin Type and Output State Nomenclature .......................................................... 12 Intel386TM EX Microprocessor Pin Descriptions ................................................. 13 Microprocessor Clocks Per Instruction................................................................ 23 Thermal Resistances (0C/W) JA, JC ................................................................ 24 5 V Intel386 EXTC Processor Maximum Ratings ............................................... 27 3 V Intel386 EXTB Processor Maximum Ratings................................................ 27 5-Volt DC Characteristics .................................................................................... 28 3-Volt DC Characteristics .................................................................................... 29 5-Volt AC Characteristics .................................................................................... 32 3-Volt AC Characteristics .................................................................................... 37
4
Datasheet
Intel386TM EX Embedded Microprocessor
Revision History
This datasheet applies to devices marked EXTB and EXTC. If you require information about devices marked EXSA or EXTA, refer to a previous revision of this datasheet, order number 272420-004.
Revision 007 006 005 004
Date 10/98 5/96 12/95 9/94
Description The document was updated to the larger page size. All known device errata for the datasheet have been incorporated into this new revision. Corrections added. This datasheet applied to the new EXTB and EXTC devices. This datasheet applied to devices marked EXSA or EXTA.
Datasheet
5
Intel386TM EX Embedded Microprocessor
1.0
Introduction
The Intel386TM EXTB embedded processor operates at 20 or 25 MHz at 3 Volts nominal. The Intel386 EXTC embedded processor operates at 25 or 33 MHz at 5 Volts. In this datasheet, "Intel386 EX processor" refers to both the Intel386 EXTB and EXTC processors. The Intel386 EX embedded processor is a highly integrated, 32-bit, fully static processor optimized for embedded control applications. With a 16-bit external data bus, a 26-bit external address bus, and Intel's System Management Mode (SMM), the Intel386 EX microprocessor brings the vast software library of Intel386 architecture to embedded systems. It provides the performance benefits of 32-bit programming with the cost savings associated with 16-bit hardware systems.
Figure 1. Intel386TM EX Embedded Processor Block Diagram
Address Data
Bus Interface Unit Chip-select Unit
JTAG Unit Address Intel386TM CX Core Core Enhancements Processor Core - A20 Gate - CPU Reset - SMM
Clock and Power Management Unit DRAM Refresh Control Unit Watchdog Timer Unit Bus Monitor Asynchronous Serial I/O 2 channels (16450 compatible) Synchronous Serial I/O 1 channel, full duplex Timer/counter Unit 3 channels (82C54 compatible)
Data
I/O Ports
INTR
Interrupt Control Unit
DMA Controller 2 channels (8237A compatible) and Bus Arbiter Unit
A2849-02
Datasheet
7
Intel386TM EX Embedded Microprocessor
2.0
Pin Assignment
Figure 2. Intel386TM EX Embedded Processor 132-Pin PQFP Pin Assignment
P2.7/CTS0# P2.6/TXD0 VSS P2.5/RXD0 DACK0#/CS5# VCC P2.4/CS4# P2.3/CS3# P2.2/CS2# P2.1/CS1# P2.0/CS0# VCC SMIACT# TRST# DRQ1/RXD1 DRQ0/DCD1# VSS CLK2 WDTOUT EOP#/CTS1# DACK1#/TXD1 P1.7/HLDA RESET VCC P1.6/HOLD P1.5/LOCK# P1.4/RI0# P1.3/DSR0# P1.2/DTR0# CLKOUT P1.1/RTS0# P1.0/DCD0# VSS
UCS# CS6#/REFRESH# VSS LBA# D0 D1 D2 D3 VCC D4 D5 D6 D7 D8 VCC D9 VSS D10 D11 D12 D13 D14 D15 TDO TDI TMS M/IO# VCC D/C# W/R# VSS READY# BS8#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
TOP VIEW
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
FLT# DSR1#/STXCLK VSS INT7/TMRGATE1 INT6/TMRCLK1 INT5/TMRGATE0 INT4/TMRCLK0 BUSY#/TMRGATE2 ERROR#/TMROUT2 NMI PEREQ/TMRCLK2 VCC P3.7/COMCLK P3.6/PWRDOWN P3.5/INT3 P3.4/INT2 VSS P3.3/INT1 VCC P3.2/INT0 RTS1#/SSIOTX RI1#/SSIORX DTR1#/SRXCLK TCK P3.1/TMROUT1/INT8 P3.0/TMROUT0/INT9 SMI# A25 VCC A24 VSS A23 A22
Note: NC = No Connection
RD# WR# VSS BLE# VCC BHE# ADS# NA# A1 A2 A3 A4 VSS VCC A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16/CAS0 VCC A17/CAS1 A18/CAS2 A19 VSS A20 A21
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
A2212-02
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 1.
132-Pin PQFP Pin Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 UCS# CS6#/REFRESH# VSS LBA# D0 D1 D2 D3 VCC D4 D5 D6 D7 D8 Symbol Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Symbol RD# WR# VSS BLE# VCC BHE# ADS# NA# A1 A2 A3 A4 VSS VCC A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16/CAS0 VCC A17/CAS1 A18/CAS2 A19 VSS A20 A21 Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 A22 A23 VSS A24 VCC A25 SMI# P3.0/TMROUT0/INT9 P3.1/TMROUT1/INT8 TCK DTR1#/SRXCLK RI1#/SSIORX RTS1#/SSIOTX Symbol Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS P1.0/DCD0# P1.1/RTS0# CLKOUT P1.2/DTR0# P1.3/DSR0# P1.4/RI0# P1.5/LOCK# P1.6/HOLD VCC RESET P1.7/HLDA DACK1#/TXD1 Symbol
80
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
P3.2/INT0
VCC P3.3/INT1 VSS P3.4/INT2 P3.5/INT3 P3.6/PWRDOWN P3.7/COMCLK VCC PEREQ/TMRCLK2 NMI ERROR#/TMROUT2 BUSY#/TMRGATE2 INT4/TMRCLK0 INT5/TMRGATE0 INT6/TMRCLK1 INT7/TMRGATE1 VSS DSR1#/STXCLK FLT#
113
114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
EOP#/CTS1#
WDTOUT CLK2 VSS DRQ0/DCD1# DRQ1/RXD1 TRST# SMIACT# VCC P2.0/CS0# P2.1/CS1# P2.2/CS2# P2.3/CS3# P2.4/CS4# VCC DACK0#/CS5# P2.5/RXD0 VSS P2.6/TXD0 P2.7/CTS0#
15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Vcc
D9 Vss D10 D11 D12 D13 D14 D15 TDO TDI TMS M/IO# VCC D/C# W/R# VSS READY# BS8#
Datasheet
9
Intel386TM EX Embedded Microprocessor
Figure 3. Intel386TM EX Embedded Processor 144-Pin TQFP Pin Assignment
VSS P2.7/CTS0# P2.6/TXD0 VSS P2.5/RXD0 DACK0#/CS5# VCC P2.4/CS4# P2.3/CS3# P2.2/CS2# P2.1/CS1# P2.0/CS0# VSS VCC SMIACT# TRST# DRQ1/RXD1 DRQ0/DCD1# VSS CLK2 WDTOUT EOP#/CTS1# DACK1#/TXD1 P1.7/HLDA VSS RESET VCC P1.6/HOLD P1.5/LOCK# P1.4/RI0# P1.3/DSR0# P1.2/DTR0# CLKOUT P1.1/RTS0# P1.0/DCD0# VSS
UCS# CS6#/REFRESH# VSS LBA# D0 D1 D2 D3 VCC D4 VSS D5 D6 D7 D8 VCC D9 VSS D10 D11 D12 D13 D14 VSS D15 TDO TDI TMS M/IO# VCC D/C# W/R# VSS READY# BS8# VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
TOP VIEW
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VSS FLT# DSR1#/STXCLK VSS INT7/TMRGATE1 INT6/TMRCLK1 INT5/TMRGATE0 INT4/TMRCLK0 BUSY#/TMRGATE2 ERROR#/TMROUT2 NMI VSS PEREQ/TMRCLK2 VCC P3.7/COMCLK P3.6/PWRDOWN P3.5/INT3 P3.4/INT2 VSS P3.3/INT1 VCC P3.2/INT0 RTS1#/SSIOTX RI1#/SSIORX DTR1#/SRXCLK VSS TCK P3.1/TMROUT1/INT8 P3.0/TMROUT0/INT9 SMI# A25 VCC A24 VSS A23 A22
RD# WR# VSS BLE# VCC BHE# ADS# NA# A1 A2 VSS A3 A4 VSS VCC A5 A6 A7 A8 A9 A10 A11 A12 VSS A13 A14 A15 A16/CAS0 VCC A17/CAS1 A18/CAS2 A19 VSS A20 A21 VSS
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
A2213-03
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 2.
144-Pin TQFP Pin Assignment
Pin 1 2 3 4 5 6 7 8 9 10 11 UCS# CS6#/REFRESH# VSS LBA# D0 D1 D2 D3 VCC D4 VSS Symbol Pin 37 38 39 40 41 42 43 44 45 46 Symbol RD# WR# VSS BLE# VCC BHE# ADS# NA# A1 A2 Pin 73 74 75 76 77 78 79 80 81 82 A22 A23 VSS A24 VCC A25 SMI# P3.0/TMROUT0/INT9 P3.1/TMROUT1/INT8 TCK Symbol Pin 109 110 111 112 113 114 115 116 117 118 VSS P1.0/DCD0# P1.1/RTS0# CLKOUT P1.2/DTR0# P1.3/DSR0# P1.4/RI0# P1.5/LOCK# P1.6/HOLD VCC Symbol
47 48 49 50
51
VSS A3 A4 VSS
VCC
83 84 85
86 87
VSS DTR1#/SRXCLK RI1#/SSIORX
RTS1#/SSIOTX P3.2/INT0
119 120 121
122 123
RESET VSS P1.7/HLDA
DACK1#/TXD1 EOP#/CTS1#
12 13 14
15 16
D5 D6 D7
D8 VCC
52 53
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
A5 A6
A7 A8 A9 A10 A11 A12 VSS A13 A14 A15 A16/CAS0 VCC A17/CAS1 A18/CAS2 A19 VSS A20 A21 VSS
88 89
90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
VCC P3.3/INT1
VSS P3.4/INT2 P3.5/INT3 P3.6/PWRDOWN P3.7/COMCLK VCC PEREQ/TMRCLK2 VSS NMI ERROR#/TMROUT2 BUSY#/TMRGATE2 INT4/TMRCLK0 INT5/TMRGATE0 INT6/TMRCLK1 INT7/TMRGATE1 VSS DSR1#/STXCLK FLT# VSS
124 125
126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
WDTOUT CLK2
VSS DRQ0/DCD1# DRQ1/RXD1 TRST# SMIACT# V CC V SS P2.0/CS0# P2.1/CS1# P2.2/CS2# P2.3/CS3# P2.4/CS4# V CC DACK0#/CS5# P2.5/RXD0 VSS P2.6/TXD0 P2.7/CTS0# VSS
17 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
D9 VSS
D10 D11 D12 D13 D14 VSS D15 TDO TDI TMS M/IO# VCC D/C# W/R# VSS READY# BS8# VSS
Datasheet
11
Intel386TM EX Embedded Microprocessor
3.0
Pin Description
Table 4 lists the Intel386 EX embedded processor pin descriptions. Table 3 defines the abbreviations used in the Type and Output States columns of Table 4.
Table 3.
Pin Type and Output State Nomenclature
Symbol Pin Type # I O I/O I/OD ST P G Output State H(1) H(0) H(Z) H(Q) H(X) R(WH) R(WL) R(1) R(0) R(Z) R(Q) R(X) I(1) I(0) I(Z) I(Q) I(X) P(1) P(0) P(Z) P(Q) P(X) Output driven to VCC during Bus Hold Output driven to VSS during Bus Hold Output floats during Bus Hold Output remains active during Bus Hold Output retains current state during Bus Hold Output Weakly Held at VCC during Reset Output Weakly Held at VSS during Reset Output driven to VCC during Reset Output driven to VSS during Reset Output floats during Reset Output remains active during Reset Output retains current state during Reset Output driven to VCC during Idle Mode Output driven to VSS during Idle Mode Output floats during Idle Mode Output remains active during Idle Mode Output retains current state during Idle Mode Output driven to VCC during Powerdown Mode Output driven to VSS during Powerdown Mode Output floats during Powerdown Mode Output remains active during Powerdown Mode Output retains current state during Powerdown Mode The named signal is active low. Standard TTL input signal. Standard CMOS output signal. Input and output signal. Input and open-drain output signal. Schmitt-triggered input signal. Power pin. Ground pin. Description
The idle mode output states assume that no internal bus master (DMA or RCU) has control of the bus during idle mode
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 4.
Intel386TM EX Microprocessor Pin Descriptions (Sheet 1 of 6)
Symbol Type Output States H(Z) R(1) I(1) P(1) H(Z) R(1) I(1) P(1) H(Z) R(0) I(X) P(0) H(Z) R(0) I(X) P(1) Name and Function Address Bus outputs physical memory or port I/O addresses. These signals are valid when ADS# is active and remain valid until the next T1, T2P, or Ti. During HOLD cycles they are driven to a high-impedance state. A18:16 are multiplexed with CAS2:0. Address Status indicates that the processor is driving a valid bus-cycle definition and address (W/R#, D/C#, M/IO#, A25:1, BHE#, BLE#) onto its pins.
A25:1
O
ADS#
O
BHE#
O
Byte High Enable indicates that the processor is transferring a high data byte.
BLE#
O
Byte Low Enable indicates that the processor is transferring a low data byte. Bus Size indicates that an 8-bit device is currently being addressed. Busy indicates that the math coprocessor is busy. If BUSY# is sampled LOW at the falling edge of RESET, the processor performs an internal self test. BUSY# is multiplexed with TMRGATE2 and has a temporary weak pull-up resistor.
BS8#
I
BUSY#
I
CAS2:0
O
H(Z) R(1) I(1) P(1)
Cascade Address carries the slave address information from the 8259A master interrupt module during interrupt acknowledge bus cycles. CAS2:0 are multiplexed with A18:16. Clock Input is connected to an external clock that provides the fundamental timing for the device.
CLK2
ST H(Q) R(Q) I(Q) P(0)
CLKOUT
O
CLKOUT is a PH1P clock output.
COMCLK
I
Serial Communications Baud Clock is an alternate clock source for the asynchronous serial ports. COMCLK is multiplexed with P3.7 and has a temporary weak pull-down resistor. H(1) R(WH) I(Q) P(X) H(1) R(1) I(Q) P(X) Chip-selects are activated when the address of a memory or I/O bus cycle is within the address region programmed by the user. They are multiplexed as follows: CS6# with REFRESH#, CS5# with DACK0#, and CS4:0# with P2.4:0. Chip-selects are activated when the address of a memory or I/O bus cycle is within the address region programmed by the user. They are multiplexed as follows: CS6# with REFRESH#, CS5# with DACK0#, and CS4:0# with P2.4:0. Clear to Send SIO1 and SIO0 prevent the transmission of data to the asynchronous serial port's RXD1 and RXD0 pins, respectively. CTS1# is multiplexed with EOP#, and CTS0# is multiplexed with P2.7. CTS1# requires an external pull-up resistor. Both have temporary weak pull-up resistors.
CS4:0#
O
CS6:5#
O
CTS1:0#
I
NOTES: 1. X if clock source is internal; Q if clock source is external 2. Q if JTAG unit is shifting out data, Z if it is not
Datasheet
13
Intel386TM EX Embedded Microprocessor
Table 4.
Intel386TM EX Microprocessor Pin Descriptions (Sheet 2 of 6)
Symbol Type Output States Name and Function Data Bus inputs data during memory read, I/O read, and interrupt acknowledge cycles and outputs data during memory and I/O write cycles. During writes, this bus is driven during phase 2 of T1 and remains active until phase 2 of the next T1, T1P, or Ti. During reads, data is latched on the falling edge of phase 2. DMA Acknowledge 1 and 0 signal to an external device that the processor has acknowledged the corresponding DMA request and is relinquishing the bus. DACK1# is multiplexed with TXD1, and DACK0# is multiplexed with CS5#. Data/Control indicates whether the current bus cycle is a data cycle (memory or I/O read or write) or a control cycle (interrupt acknowledge, halt, or code fetch). Data Carrier Detect SIO1 and SIO0 indicate that the modem or data set has detected the corresponding asynchronous serial channel's data carrier. DCD1# is multiplexed with DRQ0, and DCD0# is multiplexed with P1.0 and has a temporary weak pullup resistor. DMA External Request 1 and 0 indicate that a peripheral requires DMA service. DRQ1 is multiplexed with RXD1, and DRQ0 is multiplexed with DCD1#. Data Set Ready SIO1 and SIO0 indicate that the modem or data set is ready to establish a communication link with the corresponding asynchronous serial channel. DSR1# is multiplexed with STXCLK and has a permanent weak pull-up resistor, and DSR0# is multiplexed with P1.3 and has a temporary weak pull-up resistor. H(X) R(WH) I(X) P(X) H(Z) R(WH) I(Z) P(Z) Data Terminal Ready SIO1 and SIO0 indicate that the corresponding asynchronous serial channel is ready to establish a communication link with the modem or data set. DTR1# is multiplexed with SRXCLK, and DTR0# is multiplexed with P1.2. End of Process indicates that the processor has reached terminal count during a DMA transfer. An external device can also pull this pin LOW. EOP# is multiplexed with CTS1#. Error indicates that the math coprocessor has an error condition. ERROR# is multiplexed with TMROUT2 and has a temporary weak pull-up resistor. Float forces all bidirectional and output signals except TDO to a high-impedance state. It has a permanent weak pull-up resistor. This pin should be tied to VCC through a 3 to 7 KOhm pull-up resistor. H(1) R(WL) I(Q) P(X) Bus Hold Acknowledge indicates that the processor has surrendered control of its local bus to another bus master. HLDA is multiplexed with P1.7. Bus Hold Request allows another bus master to request control of the local bus. HLDA active indicates that bus control has been granted. HOLD is multiplexed with P1.6. It has a temporary weak pull-down resistor.
D15:0
I/O
H(Z) R(Z) P(Z)
DACK1:0#
O
H(1) R(1) I(Q) P(X) H(Z) R(1) I(0) P(0)
D/C#
O
DCD1:0
I
DRQ1:0
I
DSR1:0#
I
DTR1:0#
O
EOP#
I/OD
ERROR#
I
FLT#
I
HLDA
O
HOLD
I
NOTES: 1. X if clock source is internal; Q if clock source is external 2. Q if JTAG unit is shifting out data, Z if it is not
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 4.
Intel386TM EX Microprocessor Pin Descriptions (Sheet 3 of 6)
Symbol Type Output States Name and Function Interrupt Requests are maskable inputs that cause the CPU to suspend execution of the current program and then execute an interrupt acknowledge cycle. They are multiplexed as follows: INT9 with TMROUT0 and P3.0, INT8 with TMROUT1 and P3.1, INT7 with TMRGATE1, INT6 with TMRCLK1, INT5 with TMRGATE0, INT4 with TMRCLK0, and INT3:0 with P3.5:2. INT9, INT8, and INT3:0 have temporary weak pull-down resistors. H(1) R(1) I(Q) P(X) H(Z) R(WH) I(X) P(X) H(Z) R(0) I(1) P(1) Local Bus Access is asserted whenever the processor provides the READY# signal to terminate a bus transaction. This occurs when an internal peripheral address is accessed or when the chip-select unit provides the READY# signal. Bus Lock prevents other bus masters from gaining control of the system bus. LOCK# is multiplexed with P1.5. Memory/IO Indicates whether the current bus cycle is a memory cycle or an I/O cycle. When M/IO# is HIGH, the bus cycle is a memory cycle; when M/IO# is LOW, the bus cycle is an I/O cycle. Next Address requests address pipelining. Nonmaskable Interrupt Request is a non-maskable input that causes the CPU to suspend execution of the current program and execute an interrupt acknowledge cycle. Processor Extension Request indicates that the math coprocessor has data to transfer to the processor. PEREQ is multiplexed with TMRCLK2 and has a temporary weak pull-down resistor. H(X) R(WH) I(X) P(X) H(X) R(WL) I(X) P(X) H(X) R(WH) I(X) P(X) H(X) R(WL) I(X) P(X) H(X) R(WL) I(X) P(X) Port 1, Pins 7:0 are multipurpose bidirectional port pins. They are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD, P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#. Port 1, Pins 7:0 are multipurpose bidirectional port pins. They are multiplexed as follows: P1.7 with HLDA, P1.6 with HOLD, P1.5 with LOCK#, P1.4 with RI0#, P1.3 with DSR0#, P1.2 with DTR0#, P1.1 with RTS0#, and P1.0 with DCD0#. Port 2, Pins 7:0 are multipurpose bidirectional port pins. They are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0, P2.5 with RXD0, and P2.4:0 with CS4:0#. Port 2, Pins 7:0 are multipurpose bidirectional port pins. They are multiplexed as follows: P2.7 with CTS0#, P2.6 with TXD0, P2.5 with RXD0, and P2.4:0 with CS4:0#. Port 3, Pins 7:0 are multipurpose bidirectional port pins. They are multiplexed as follows: P3.7 with COMCLK, P3.6 with PWRDOWN, P3.5:2 with INT3:0, and P3.1:0 with TMROUT1:0 and INT8:9.
INT9:0
I
LBA#
O
LOCK#
O
M/IO#
O
NA# NMI
I ST
PEREQ
I
P1.5:0
I/O
P1.7:6
I/O
P2.7,4:0
I/O
P2.6:5
I/O
P3.7:0
I/O
NOTES: 1. X if clock source is internal; Q if clock source is external 2. Q if JTAG unit is shifting out data, Z if it is not
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Intel386TM EX Embedded Microprocessor
Table 4.
Intel386TM EX Microprocessor Pin Descriptions (Sheet 4 of 6)
Symbol Type Output States H(Q) R(WL) I(X) P(1) H(1) R(1) I(1) P(1) H(Z) R(Z) I(Z) P(Z) Name and Function Powerdown indicates that the processor is in powerdown mode. PWRDOWN is multiplexed with P3.6.
PWRDOWN
O
RD#
O
Read Enable indicates that the current bus cycle is a read cycle.
READY#
I/O
Ready indicates that the current bus transaction has completed. An external device or an internal signal can drive READY#. Internally, the chip-select wait-state logic can generate the ready signal and drive the READY# pin active. Reset suspends any operation in progress and places the processor into a known reset state.
RESET
ST H(1) R(1) I(Q) P(X)
REFRESH#
O
Refresh indicates that the current bus cycle is a refresh cycle. REFRESH# is multiplexed with CS6#. Ring Indicator SIO1 and SIO0 indicate that the modem or data set has received a telephone ringing signal. RI1# is multiplexed with SSIORX, and RI0# is multiplexed with P1.4 and has a temporary weak pull-up resistor.
RI1:0#
I
RTS1#
O
H(X) R(WL) I(X) P(X) H(X) R(WH) I(X) P(X)
Request-to-send SIO1 and SIO0 indicate that corresponding asynchronous serial channel is ready to exchange data with the modem or data set. RTS1# is multiplexed with SSIOTX, and RTS0# is multiplexed with P1.1. Request-to-send SIO1 and SIO0 indicate that corresponding asynchronous serial channel is ready to exchange data with the modem or data set. RTS1# is multiplexed with SSIOTX, and RTS0# is multiplexed with P1.1. Receive Data SIO1 and SIO0 accept serial data from the modem or data set to the corresponding asynchronous serial channel. RXD1 is multiplexed with DRQ1, and RXD0 is multiplexed with P2.5 and has a temporary weak pull-down resistor. System Management Interrupt invokes System Management Mode (SMM). SMI# is the highest priority external interrupt. It is latched on its falling edge and forces the CPU into SMM upon completion of the current instruction. SMI# is recognized on an instruction boundary and at each iteration for repeat string instructions. SMI# cannot interrupt LOCKed bus cycles or a currently executing SMM. When the processor receives a second SMI# while in SMM, it latches the second SMI# on the SMI# falling edge. However, the processor must exit SMM by executing a resume instruction (RSM) before it can service the second SMI#. SMI# has a permanent weak pull-up resistor.
RTS0#
O
RXD1:0
I
SMI#
ST
SMIACT#
O
H(1) R(1) I(X) P(X)
System Management Interrupt Active indicates that the processor is operating in System Management Mode (SMM). It is asserted when the processor initiates an SMM sequence and remains asserted (LOW) until the processor executes the resume instruction (RSM).
NOTES: 1. X if clock source is internal; Q if clock source is external 2. Q if JTAG unit is shifting out data, Z if it is not
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Intel386TM EX Embedded Microprocessor
Table 4.
Intel386TM EX Microprocessor Pin Descriptions (Sheet 5 of 6)
Symbol Type Output States H(Q) R(WH) I(Q) P(X)/P(Q)Note 1 Name and Function SSIO Receive Clock synchronizes data being accepted by the synchronous serial port. SRXCLK is multiplexed with DTR1#. SSIO Receive Serial Data accepts serial data (most-significant bit first) being sent to the synchronous serial port. SSIORX is multiplexed with RI1#. H(Q) R(WL) I(Q) P(X)/P(Q)Note 1 H(Q) R(WH) I(Q) P(X)/P(Q)Note 1 SSIO Transmit Serial Data sends serial data (most-significant bit first) from the synchronous serial port. SSIOTX is multiplexed with RTS1#. Intel does not specify a data hold time for SSIOTX. Slower external devices may require additional hardware to properly interface the SSIO unit. SSIO Transmit Clock synchronizes data being sent by the synchronous serial port. STXCLK is multiplexed with DSR1. TAP (Test Access Port) Controller Clock provides the clock input for the JTAG logic. It has a permanent weak pull-up resistor. TAP (Test Access Port) Controller Data Input is the serial input for test instructions and data. It has a permanent weak pullup resistor. H(Z)/H(Q)Note 2 R(Z)/R(Q)Note 2 I(Z)/I(Q)Note 2 P(Z)/ P(Q) Note 2 TAP (Test Access Port) Controller Data Output is the serial output for test instructions and data. Timer/Counter Clock Inputs can serve as external clock inputs for the corresponding timer/counters. (The timer/counters can also be clocked internally.) They are multiplexed as follows: TMRCLK2 with PEREQ, TMRCLK1 with INT6, and TMRCLK0 with INT4. TMRCLK2 has a temporary weak pull-down resistor. Timer/Counter Gate Inputs can control the corresponding timer/counter's counting (enable, disable, or trigger, depending on the programmed mode). They are multiplexed as follows: TMRGATE2 with BUSY#, TMRGATE1 with INT7, and TMRGATE0 with INT5. TMRGATE2 has a temporary weak pullup resistor. H(Q) R(WH) I(Q) P(X)/P(Q)Note 1 H(Q) R(WL) I(Q) P(X)/P(Q)Note 1 Timer/Counter Outputs provide the output of the corresponding timer/counter. The form of the output depends on the programmed mode. They are multiplexed as follows: TMROUT2 with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0 with P3.0 and INT9. Timer/Counter Outputs provide the output of the corresponding timer/counter. The form of the output depends on the programmed mode. They are multiplexed as follows: TMROUT2 with ERROR#, TMROUT1 with P3.1 and INT8, and TMROUT0 with P3.0 and INT9. TAP (Test Access Port) Controller Mode Select controls the sequence of the TAP controller's states. It has a permanent weak pull-up resistor.
SRXCLK
I/O
SSIORX
I
SSIOTX
O
STXCLK
I/O
TCK
I
TDI
I
TDO
O
TMRCLK2:0
I
TMRGATE2:0
I
TMROUT2
O
TMROUT1:0
O
TMS
I
NOTES: 1. X if clock source is internal; Q if clock source is external 2. Q if JTAG unit is shifting out data, Z if it is not
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Intel386TM EX Embedded Microprocessor
Table 4.
Intel386TM EX Microprocessor Pin Descriptions (Sheet 6 of 6)
Symbol TRST# Type ST H(Q) R(1) I(Q) P(X)/P(Q)Note 1 H(Q) R(WL) I(Q) P(X)/P(Q)Note 1 H(1) R(0) I(Q) P(X) Output States Name and Function TAP (Test Access Port) Controller Reset resets the TAP controller at power-up and each time it is activated. It has a permanent weak pull-up resistor. Transmit Data SIO1 and SIO0 transmit serial data from the individual serial channels. TXD1 is multiplexed with DACK1#, and TXD0 is multiplexed with P2.6. Transmit Data SIO1 and SIO0 transmit serial data from the individual serial channels. TXD1 is multiplexed with DACK1#, and TXD0 is multiplexed with P2.6. Upper Chip-select is activated when the address of a memory or I/O bus cycle is within the address region programmed by the user. System Power provides the nominal DC supply input. This pin is connected externally to a VCC board plane. System Ground provides the 0 V connection from which all inputs and outputs are measured. This pin is connected externally to a ground board plane. H(Q) R(0) I(Q) P(X) H(Z) R(0) I(1) P(1) H(1) R(1) I(1) P(1) Watchdog Timer Output indicates that the watchdog timer has expired.
TXD1
O
TXD0
O
UCS#
O
VCC
P
VSS
G
WDTOUT
O
W/R#
O
Write/Read indicates whether the current bus cycle is a write cycle or a read cycle. When W/R# is HIGH, the bus cycle is a write cycle; when W/R# is LOW, the bus cycle is a read cycle.
WR#
O
Write Enable indicates that the current bus cycle is a write cycle.
NOTES: 1. X if clock source is internal; Q if clock source is external 2. Q if JTAG unit is shifting out data, Z if it is not
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Datasheet
Intel386TM EX Embedded Microprocessor
4.0
Functional Description
The Intel386 EX microprocessor is a fully static, 32-bit processor optimized for embedded applications. It features low power and low voltage capabilities, integration of many commonly used DOS-type peripherals, and a 32-bit programming architecture compatible with the large software base of Intel386 processors. The following sections provide an overview of the integrated peripherals.
4.1
Clock Generation and Power Management Unit
The clock generation circuit includes a divide-by-two counter, a programmable divider for generating a prescaled clock (PSCLK), a divide-by-two counter for generating baud-rate clock inputs, and Reset circuitry. The CLK2 input provides the fundamental timing for the chip. It is divided by two internally to generate a 50% duty cycle Phase1 (PH1) and Phase 2 (PH2) for the core and integrated peripherals. For power management, separate clocks are routed to the core (PH1C/PH2C) and the peripheral modules (PH1P/PH2P). To help synchronize with external devices, the PH1P clock is provided on the CLKOUT output pin. Two Power Management modes are provided for flexible power-saving options. During Idle mode, the clocks to the CPU core are frozen in a known state (PH1C low and PH2C high), while the clocks to the peripherals continue to toggle. In Powerdown mode, the clocks to both core and peripherals are frozen in a known state (PH1C low and PH2C high). The Bus Interface Unit will not honor any DMA, DRAM refresh, or HOLD requests in Powerdown mode because the clocks to the entire device are frozen.
4.2
Chip-select Unit
The Chip-Select Unit (CSU) decodes bus cycle address and status information and enables the appropriate chip-selects. The individual chip-selects become valid in the same bus state as the address and become inactive when either a new address is selected or the current bus cycle is complete. The CSU is divided into eight separate chip-select regions, each of which can enable one of the eight chip-select pins. Each chip-select region can be mapped into memory or I/O space. A memory-mapped chip-select region can start on any 2(n+1) Kbyte address location (where n = 0-15, depending upon the mask register). An I/O-mapped chip-select region can start on any 2(n+1) byte address location (where n = 0-15, depending upon the mask register). The size of the region is also dependent upon the mask used.
4.3
Interrupt Control Unit
The Intel386 EX processor's Interrupt Control Unit (ICU) contains two 8259A modules connected in a cascade mode. These modules are similar to the industry-standard 8259A architecture. The Interrupt Control Unit directly supports up to ten external (INT9:0) and up to eight internal interrupt request signals. Pending interrupt requests are posted in the Interrupt Request Registers, which contain one bit for each interrupt request signal. When an interrupt request is asserted, the corresponding Interrupt Request Register bit is set. The 8259A modules can be programmed to
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Intel386TM EX Embedded Microprocessor
recognize either an active-high level or a positive transition on the interrupt request lines. An internal Priority Resolver decides which pending interrupt request (if more than one exists) is the highest priority, based on the programmed operating mode. The Priority Resolver controls the single interrupt request line to the CPU. The Priority Resolver's default priority scheme places the master interrupt controller's IR0 as the highest priority and the master's IR7 as the lowest. The priority can be modified through software. Besides the ten interrupt request inputs available to the Intel386 EX microprocessor, additional interrupts can be supported by cascaded external 8259A modules. Up to four external 8259A units can be cascaded to the master through connections to the INT3:0 pins. In this configuration, the interrupt acknowledge (INTA#) signal can be decoded externally using the ADS#, D/C#, W/R#, and M/IO# signals.
4.4
Timer/Counter Unit
The Timer/Counter Unit (TCU) on the Intel386 EX microprocessor has the same basic functionality as the industry-standard 82C54 counter/timer. The TCU provides three independent 16-bit counters, each capable of handling clock inputs up to 8 MHz. This maximum frequency must be considered when programming the input clocks for the counters. Six programmable timer modes allow the counters to be used as event counters, elapsed-time indicators, programmable oneshots, and in many other applications. All modes are software programmable.
4.5
Watchdog Timer Unit
The Watchdog Timer (WDT) unit consists of a 32-bit down-counter that decrements every PH1P cycle, allowing up to 4.3 billion count intervals. The WDTOUT pin is driven high for sixteen CLK2 cycles when the down-counter reaches zero (the WDT times out). The WDTOUT signal can be used to reset the chip, to request an interrupt, or to indicate to the user that a ready-hang situation has occurred. The down-counter can also be updated with a user-defined 32-bit reload value under certain conditions. Alternatively, the WDT unit can be used as a bus monitor or as a general-purpose timer.
4.6
Asynchronous Serial I/O Unit
The Intel386 EX microprocessor's asynchronous Serial I/O (SIO) unit is a Universal Asynchronous Receiver/ Transmitter (UART). Functionally, it is equivalent to the National Semiconductor NS16450 and INS8250. The Intel386 EX embedded processor contains two fullduplex, asynchronous serial channels. The SIO unit converts serial data characters received from a peripheral device or modem to parallel data and converts parallel data characters received from the CPU to serial data. The CPU can read the status of the serial port at any time during its operation. The status information includes the type and condition of the transfer operations being performed and any errors (parity, framing, overrun, or break interrupt).
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Datasheet
Intel386TM EX Embedded Microprocessor
Each asynchronous serial channel includes full modem control support (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#) and is completely programmable. The programmable options include character length (5, 6, 7, or 8 bits), stop bits (1, 1.5, or 2), and parity (even, odd, forced, or none). In addition, it contains a programmable baud-rate generator capable of clock rates from 0 to 512 Kbaud.
4.7
Synchronous Serial I/O Unit
The Synchronous Serial I/O (SSIO) unit provides for simultaneous, bidirectional communications. It consists of a transmit channel, a receive channel, and a dedicated baud-rate generator. The transmit and receive channels can be operated independently (with different clocks) to provide non-lockstep, full-duplex communications; either channel can originate the clocking signal (Master Mode) or receive an externally generated clocking signal (Slave Mode). The SSIO provides numerous features for ease and flexibility of operation. With a maximum clock input of CLK2/4 to the baud-rate generator, the SSIO can deliver a baud rate of up to 8.25 Mbits per second with a processor clock of 33 MHz. Each channel is double buffered. The two channels share the baud-rate generator and a multiply-by-two transmit and receive clock. The SSIO supports 16-bit serial communications with independently enabled transmit and receive functions and gated interrupt outputs to the interrupt controller.
4.8
Parallel I/O Unit
The Intel386 EX microprocessor has three 8-bit, general-purpose I/O ports. All port pins are bidirectional, with TTL-level inputs and CMOS-level outputs. All pins have both a standard operating mode and a peripheral mode (a multiplexed function), and all have similar sets of control registers located in I/O address space.
4.9
DMA and Bus Arbiter Unit
The Intel386 EX microprocessor's DMA controller is a two-channel DMA; each channel operates independently of the other. Within the operation of the individual channels, several different data transfer modes are available. These modes can be combined in various configurations to provide a very versatile DMA controller. Its feature set has enhancements beyond the 8237 DMA family; however, it can be configured such that it can be used in an 8237-like mode. Each channel can transfer data between any combination of memory and I/O with any combination (8 or 16 bits) of data path widths. An internal temporary register that can disassemble or assemble data to or from either an aligned or a nonaligned destination or source optimizes bus bandwidth. The bus arbiter, a part of the DMA controller, works much like the priority resolving circuitry of a DMA. It receives service requests from the two DMA channels, the external bus master, and the DRAM Refresh Control Unit. The bus arbiter requests bus ownership from the core and resolves priority issues among all active requests when bus mastership is granted. Each DMA channel consists of three major components: the Requestor, the Target, and the Byte Count. These components are identified by the contents of programmable registers that define the memory or I/O device being serviced by the DMA. The Requestor is the device that requires and requests service from the DMA controller. Only the Requestor is considered capable of initializing
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Intel386TM EX Embedded Microprocessor
or terminating a DMA process. The Target is the device with which the Requestor wishes to communicate. The DMA process considers the Target a slave that is incapable of controlling the process. The Byte Count dictates the amount of data that must be transferred.
4.10
Refresh Control Unit
The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrated address and clock counters. Integrating the RCU into the processor allows an external DRAM controller to use chip-selects, wait state logic, and status lines. The Refresh Control Unit:
* * * *
Provides a programmable-interval timer Provides the bus arbitration logic to gain control of the bus to run refresh cycles Contains the logic to generate row addresses to refresh DRAM rows individually Contains the logic to signal the start of a refresh cycle
The RCU contains a 13-bit address counter that forms the refresh address, supporting DRAMs with up to 13 rows of memory cells (13 refresh address bits). This includes all practical DRAM sizes for the Intel386 EX microprocessor's 64 Mbyte address space.
4.11
JTAG Test-logic Unit
The JTAG Test-logic Unit provides access to the device pins and to a number of other testable areas on the device. It is fully compliant with the IEEE 1149.1 standard and thus interfaces with five dedicated pins: TRST#, TCK, TMS, TDI, and TDO. It contains the Test Access Port (TAP) finitestate machine, a 4-bit instruction register, a 32-bit identification register, and a single-bit bypass register. The test-logic unit also contains the necessary logic to generate clock and control signals for the Boundary Scan chain. Since the test-logic unit has its own clock and reset signals, it can operate autonomously. While the rest of the microprocessor is in Reset or Powerdown, the JTAG unit can read or write various register chains.
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Intel386TM EX Embedded Microprocessor
5.0
Design Considerations
This section describes the Intel386 EX microprocessor's instruction set and its component and revision identifiers.
5.1
Instruction Set
The Intel386 EX microprocessor uses the same instruction set as the Intel386 SX microprocessor with the following exceptions. The Intel386 EX microprocessor has one new instruction (RSM). This Resume instruction causes the processor to exit System Management Mode (SMM). RSM requires 338 clocks per instruction (CPI). The Intel386 EX microprocessor requires more clock cycles than the Intel386 SX microprocessor to execute some instructions. Table 5 lists these instructions and the Intel386 EX microprocessor clock count. For the equivalent Intel386 SX microprocessor clock count, refer to the "Instruction Set Clock Count Summary" table in the Intel386TM SX Microprocessor datasheet (order number 240187).
Table 5.
Microprocessor Clocks Per Instruction
Clock Count Instruction Virtual 8086 Mode(2) POPA IN: Fixed Port Variable Port OUT: Fixed Port Variable Port INS OUTS REP INS REP OUTS HLT MOV CR0, reg 27 28 27 28 30 31 31+6n
(Note 4) (1)
Real Address Mode or Virtual 8086 Mode 29 14 15 14 15 17 18 17+7n
(Note 4)
Protected Virtual Address Mode(3) 35 8/29 9/29 8/29 9/29 10/32 11/33 11+7n/32+6n (Note 4) 10+8n/31+8n (Note 4) 7 10
30+8n (Note 4)
16+8n (Note 4) 7 10
NOTES: 1. For IN, OUT, INS, OUTS, REP INS, and REP OUTS instructions, add one clock count for each wait state generated by the peripheral being accessed (the values in the table are for zero wait state). 2. The clock count values in this column apply if I/O permission allows I/O to the port in virtual 8086 mode. If the I/O bit map denies permission, exception fault 13 occurs; see clock counts for the INT 3 instruction in the "Instruction Set Clock Count Summary" table in the Intel386TM SX Microprocessor datasheet (order number 240187). 3. When two clock counts are listed, the smaller value refers to the case where CPL IOPL and the larger value refers to the case where CPL>IOPL. CPL is the current privilege level, and IOPL is the I/O privilege level. 4. n = the number of times repeated.
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Intel386TM EX Embedded Microprocessor
5.2
Component and Revision Identifiers
To assist users, the microprocessor holds a component identifier and revision identifier in its DX register after reset. The upper 8 bits of DX hold the component identifier, 23H. (The lower nibble, 3H, identifies the Intel386 architecture, while the upper nibble, 2H, identifies the second member of the Intel386 microprocessor family.) The lower 8 bits of DX hold the revision level identifier. The revision identifier will, in general, chronologically track those component steppings that are intended to have certain improvements or distinction from previous steppings. The revision identifier will track that of the Intel386 CPU whenever possible. However, the revision identifier value is not guaranteed to change with every stepping revision or to follow a completely uniform numerical sequence, depending on the type or intent of the revision or the manufacturing materials required to be changed. Intel has sole discretion over these characteristics of the component. The initial revision identifier for the Intel386 EX microprocessor is 09H.
5.3
Package Thermal Specifications
The Intel386 EX microprocessor is specified for operation with a minimum case temperature (TCASE(MIN)) of -40 C and a maximum case temperature (TCASE(MAX)) dependent on power dissipation (see Figures 4 through 7). The case temperature can be measured in any environment to determine whether the microprocessor is within the specified operating range. The case temperature should be measured at the center of the top surface opposite the pins. An increase in the ambient temperature (TA) causes a proportional increase in the case temperature (TCASE) and the junction temperature (TJ), which is the junction temperature on the die itself. A packaged device produces thermal resistance between junction and case temperatures (JC) and between junction and ambient temperatures (JA). The relationships between the temperature and thermal resistance parameters are expressed by these equations: TJ = TCASE + P x JC TA = TJ - P x JA TCASE = TA + P x [JA - JC] P = power dissipated as heat = V CC x ICC A safe operating temperature can be calculated from the above equations by using the maximum safe TJ of 120 C, the power drawn by the chip in the specific design, and the JC value from Table 6. The JA value depends on the airflow (measured at the top of the chip) provided by the system ventilation, board layout, board thickness, and potentially other factors in the design of the application. The JA values are given for reference only and are not guaranteed.
Table 6.
Thermal Resistances (0C/W) JA, JC
Package 132 PQFP 144 TQFP JC 0 7 4 28 36 JA vs. Airflow (ft/min) 100 24 31 200 22 27
Figures 4 through 7 provide maximum case temperature as a function of frequency.
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Datasheet
Intel386TM EX Embedded Microprocessor
Figure 4. Maximum Case Temperature vs. Frequency for Typical Power Values (132-lead PQFP, VCC = 5.5 V)
114 113 112.25 112 111 113.9
132 Lead PQFP
Tc (deg C)
110.7
110 109 108 107 107.8
16
20
25
33
Operating Frequency (MHz)
A3346-02
Figure 5. Maximum Case Temperature vs. Frequency for Typical Power Values (144-lead TQFP, V CC = 5.5 V nominal)
116 115 114 113.5 113 Tc 112 (deg C) 111 110 109 108 109.8 112.25 114.9
144 Lead TQFP
16
20
25
33
Operating Frequency (MHz)
A3347-02
Datasheet
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Intel386TM EX Embedded Microprocessor
Figure 6. Maximum Case Temperature vs. Frequency for Typical Power Values (132-lead PQFP, V CC = 3.6 V)
117.5
117.5
132 Lead PQFP
117.0 117.0 Tc (deg C)
116.5
116.5
16
20
25
Operating Frequency (MHz)
A3348-02
Figure 7. Maximum Case Temperature vs. Frequency for Typical Power Values (144-lead TQFP, V CC = 3.6 V)
118.0
118.0
144 Lead TQFP
117.5 117.5 Tc (deg C)
117.0
117.0
16
20
25
Operating Frequency (MHz)
A3349-01
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Intel386TM EX Embedded Microprocessor
6.0
6.1
Warning:
Electrical Specifications
Maximum Ratings
Stressing the device beyond the "Maximum Ratings" may cause permanent damage. These are stress ratings only. 5 V Intel386 EXTC Processor Maximum Ratings
Parameter Storage Temperature Supply Voltage with Respect to VSS Voltage on Other Pins VCC (Digital Supply Voltage) TCASE (Case Temperature Under Bias) TCASE(MIN) TCASE(MAX) FOSC (Operating Frequency) -40C (see Figures 4 and 5) 0 MHz to 33 MHz Maximum Rating -65C to +150C -0.5 V to 6.5 V -0.5 V to VCC + 0.5 V 4.5 V to 5.5 V
Table 7.
Table 8.
3 V Intel386 EXTB Processor Maximum Ratings
Parameter Storage Temperature Supply Voltage with Respect to VSS Voltage on Other Pins VCC (Digital Supply Voltage) TCASE (Case Temperature Under Bias) TCASE(MIN) TCASE(MAX) FOSC (Operating Frequency) -40C (see Figures 6 and 7) 0 MHz to 25 MHz Maximum Rating -65C to +150C -0.5 V to 4.6 V -0.5 V to VCC + 0.5 V 20 MHz -- 2.7 V to 3.6 V 25 MHz -- 3.0 V to 3.6 V
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Intel386TM EX Embedded Microprocessor
6.2
Table 9.
DC Specifications
5-Volt DC Characteristics
Symbol V IL Parameter Input Low Voltage for all input pins except CLK2, TRST#, RESET, SMI#, and NMI Input High Voltage for all input pins except CLK2, TRST#, RESET, SMI#, and NMI Input Low Voltage for CLK2, TRST#, RESET, SMI#, and NMI Input High Voltage for CLK2, TRST#, RESET, SMI#, and NMI Output Low Voltage VOL All pins except Port 3 Port 3 Output High Voltage All output pins All pins except Port 3 Port 3 pins (2 max) CLKOUT CLKOUT Input Leakage Current Output Leakage Current V CC-0.5 2.45 15 15 320 250 ICC Supply Current V CC-0.5 2.45 2.45 0.45 0.45 0.45 V V V V V V V A A mA mA IOL = 8 mA IOL = 16 mA IOH = -0.2 mA IOH = -8 mA IOH = -16 mA IOL = 2 mA IOH = -0.2 mA IOH = -2 mA 0 VIN VCC FLT# is not tested for ILI 0.45V VOUT VCC FOSC =33 MHz FOSC =25 MHz (tested with device held in reset, inputs held in their inactive state) FOSC =33 MHz FOSC =25 MHz Min. -0.3 Max. 0.8 Unit V Test Condition
VIH VILC VIHC
2.0
VCC + 0.3 0.8 VCC+0.3
V
-0.3 V CC-0.8
V V
VOH VOLC VOHC ILI ILO
IIDLE IPD CS
Idle Mode Current Powerdown Current Pin Capacitance (any pin to VSS)
110 85 100 10
mA mA A pF
Not tested
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 10. 3-Volt DC Characteristics
Symbol Parameter Input Low Voltage for all input pins except CLK2, TRST#, RESET, SMI#, and NMI Input High Voltage for all input pins except CLK2, TRST#, RESET, SMI#, and NMI Input Low Voltage for CLK2, TRST#, RESET, SMI#, and NMI Input High Voltage for CLK2, TRST#, RESET, SMI#, and NMI Output Low Voltage VOL All pins except Port 3 Port 3 pins (2 max) Output High Voltage VOH All pins except Port 3 Port 3 CLKOUT VCC -0.2 VCC -0.65 VCC -0.65 0.2 0.45 VCC -0.2 VCC -0.65 5 15 140 110 Min. Max. Unit Test Condition
VIL
-0.3
0.8
V
VIH
2.0
V CC + 0.3
V
VILC
-0.3
0.8
V
VIHC
VCC -0.6
VCC+0.3 0.20 0.45 0.45
V V V V V V V V IOL = 100 A, 2.7 V V CC 3.6 V (LVCMOS) IOL = 4mA, 3.0 VVCC3.6 V (LVTTL) IOL = 8mA, 3.0 VVCC3.6 V (LVTTL) IOH= -100 A, 2.7 VVCC 3.6 V (LVCMOS) IOH= -4mA, 3.0 VVCC 3.6V (LVTTL) IOH= -8mA, 3.0 VVCC 3.6V (LVTTL) IOL = 100 A, 2.7 V V CC 3.6 V IOL = 1 mA, 3.0 V VCC 3.6 V (LVTTL) IOH = -100 A, 2.7 V VCC 3.6 V IOH = -1 mA, 3.0 V VCC 3.6 V (LVTTL) 0 VIN VCC FLT# is not tested for ILI 0.45V VOUT VCC FOSC = 25 MHz, VCC=3.6 V FOSC = 20 MHz, VCC=3.6 V (tested with device held in reset, inputs held in their inactive state)
VOLC
VOHC ILI ILO
CLKOUT
V
Input Leakage Current Output Leakage Current
A A mA mA
ICC
Supply Current
IIDLE IPD CS
Idle Mode Current Powerdown Current Pin Capacitance (any pin to V SS)
50 40 100 10
mA mA A pF
FOSC = 25 MHz, VCC=3.6 V FOSC = 20 MHz, VCC=3.6 V
Not tested
Datasheet
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Intel386TM EX Embedded Microprocessor
6.3
AC Specifications
Table 11 lists output delays, input setup requirements, and input hold requirements for the 5 V EXTC processor; Table 12 is for the EXTB processor. All AC specifications are relative to the CLK2 rising edge crossing the VCC/2 level for the EXTB, or 2.0 Volts for the EXTC. Figures 8 and 9 show the measurement points for AC specifications for the EXTB and EXTC processors. Inputs must be driven to the indicated voltage levels when AC specifications are measured. Output delays are specified with minimum and maximum limits measured as shown. The minimum delay times are hold times provided to external circuitry. Input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. Within the sampling window, a synchronous input signal must be stable for correct operation. Outputs ADS#, W/R#, CS5:0#, UCS#, D/C#, M/IO#, LOCK#, BHE#, BLE#, REFRESH#/CS6#, READY#, LBA#, A25:1, HLDA and SMIACT# change only at the beginning of phase one. D15:0 (write cycles) and PWRDOWN change only at the beginning of phase two. RD# and WR# change to their active states at the beginning of phase two. RD# changes to its inactive state (end of cycle) at the beginning of phase one. See the Intel386TM EX Embedded Microprocessor User's Manual for a detailed explanation of early READY# vs. late READY#. The READY#, HOLD, BUSY#, ERROR#, PEREQ, BS8#, and D15:0 (read cycles) inputs are sampled at the beginning of phase one. The NA#, SMI#, and NMI inputs are sampled at the beginning of phase two.
Figure 8. Drive Levels and Measurement Points for AC Specifications (EXTC)
PH1 CLK2 b A OUTPUTS (A25:1,BHE# BLE#,ADS#,M/IO# D/C#W/R#,LOCK# HLDA, SMIACT#) B Min Valid a Output n Max a Valid Output n+1 A B Min OUTPUTS (D15:0) Valid a Output n C INPUTS (N/A#,INTR NMI,SMI#) INPUTS (READY#,HOLD FLT#,ERROR# BUSY#,PEREQ D15:0,A20) LEGEND a - VCC /2 b - 2.0V c = 1.5V A - Maximum Output Delay Spec B - Minimum Output Delay Spec C - Minimum Input Setup Spec D - Minimum Input Hold Spec 3.0V 0V c Valid Input D c C 3.0V 0V c Valid Input D c Max a Valid Output n+1 Tx PH2
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Datasheet
Intel386TM EX Embedded Microprocessor
Figure 9. Drive Levels and Measurement Points for AC Specifications (EXTB)
PH1 CLK2 a A OUTPUTS (A25:1,BHE# BLE#,ADS#,M/IO# D/C#W/R#,LOCK# HLDA, SMIACT#) B Min Valid a Output n Max a Valid Output n+1 A B Min OUTPUTS (D15:0) Valid a Output n C INPUTS (N/A#,INTR NMI,SMI#) INPUTS (READY#,HOLD FLT#,ERROR# BUSY#,PEREQ D15:0,A20) LEGEND a - VCC/2 b = 1.5V A - Maximum Output Delay Spec B - Minimum Output Delay Spec C - Minimum Input Setup Spec D - Minimum Input Hold Spec
A2600-02
Tx
PH2
Max a Valid Output n+1
D Valid Input b C 2.0V 0V b Valid Input D b
2.0V 0V
b
Datasheet
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Intel386TM EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 1 of 5)
33 MHz Symbol Parameter Min. (ns) 0 15 6.25 4 6.25 4.5 4 4 4 4 4 4 4 4 4 4 21 28 21 21 28 21 18 28 4 4 4 4 4 4 4 4 Max. (ns) 33 25 MHz Min. (ns) 0 20 7 4 7 5 7 7 24 28 24 24 28 24 22 28 (6) (2) (2) (2) (2) (2) (2) CL = 50 pF (3) CL = 50 pF CL = 50 pF (3) CL = 50 pF Max. (ns) 25 Test Condition
Operating Frequency t1 t2a t2b t3a t3b t4 t5 t6 t7 t8 t8a t9 t10 t10a t10b t11 t12 t13 t14 t15 t16 t19 t19a CLK2 Period CLK2 High Time CLK2 High Time CLK2 Low Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A25:1 Valid Delay A25:1 Float Delay BHE#, BLE#, LOCK# Valid Delay SMIACT# Valid Delay BHE#, BLE#, LOCK# Float Delay M/IO#, D/C#, W/R#, ADS#, REFRESH# Valid Delay RD#, WR# Valid Delay WR# Valid Delay for the rising edge with respect to phase two (external late READY#) M/IO#, D/C#, W/R#, REFRESH#, ADS# Float Delay D15:0 Write Data Valid Delay D15:0 Write Data Float delay HLDA Valid Delay NA# Setup Time NA# Hold Time READY# Setup Time BS8# Setup Time
one-half CLK2 frequency in MHz (1)
4 4 4 4 5 3 8 11
28 23 22 18
4 4 4 4 5 3 9 11
28 23 22 22
(3) CL = 50 pF (3) CL = 50 pF
NOTE: 1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 2 of 5)
33 MHz Symbol Parameter Min. (ns) 4 7 4 8 3 5 2 6 6 6 6 6 5 4 4 4 4 2 4 0 0 0 0 10 24 34 20 24 (25 in SMM) 9 15 Max. (ns) 25 MHz Min. (ns) 4 7 4 8 3 5 3 6 6 6 6 6 5 4 4 4 4 2 4 0 0 0 0 10 (7, 8) (6) 26 34 22 30 14 18 CL = 30 pF CL = 30 pF (4) (4) (4) (4) (4) (4) CL = 30 pF Max. (ns) Test Condition
t20 t21 t22 t23 t24 t25 t26 t27 t27a t28 t28a t29 t30 t31 t32 t33 t34 t35 t36 t41 t41a t42 t42a t42b
READY#, BS8# Hold Time D15:0 Read Setup Time D15:0 Read Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI Setup Time SMI# Setup Time NMI Hold Time SMI# Hold Time PEREQ, ERROR#, BUSY# Setup Time PEREQ, ERROR#, BUSY# Hold Time READY# Valid Delay READY# Float Delay LBA# Valid Delay CS6:0#, UCS# Valid Delay CLKOUT Valid Delay PWRDOWN Valid Delay A25:1, BHE#, BLE# Valid to WR# Low UCS#, CS6:0# Valid to WR# Low A25:1, BHE#, BLE# Hold After WR# High UCS#, CS6:0# Hold after WR# High A25:1. BHE#, BLE# Hold After WR# High
NOTE: 1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
Datasheet
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Intel386TM EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 3 of 5)
33 MHz Symbol Parameter Min. (ns) 2CLK2 -10 CLK2 -10 CLK2 + 10 2CLK2 -10 4CLK2 28 4CLK2 31 3CLK2 - 25 0 CLK2 0 0 3CLK2 -10 0 0 3CLK2 -10 0 CLK2 (3) 2CLK2 -10 Max. (ns) 25 MHz Min. (ns) 2CLK2 - 10 CLK2 -10 CLK2 + 10 (3) (7) 4CLK2(5) 31 4CLK2 (5) 35 3CLK2 - (5) 29 Max. (ns) (5) Test Condition
t43 t44 t45 t46 t47 t47a t48 t49 t50 t51 t51a t52
D15:0 Output Valid to WR# High D15:0 Output Hold After WR# High WR# High to D15:0 Float WR# Pulse Width A25:1, BHE#, BLE# Valid to D15:0 Valid UCS#, CS6:0# Valid to D15-D0 Valid RD# Low to D15:0 Input Valid D15:0 Hold After RD# High RD# High to D15:0 Float A25:1, BHE#, BLE# Hold After RD# High UCS#, CS6:0# Hold after RD# High RD# Pulse Width
Synchronous Serial I/O (SSIO) Unit t100 t101 t102 t103 t104 t105 t106 STXCLK, SRXCLK Frequency (Master Mode) STXCLK, SRXCLK Frequency (Slave Mode) STXCLK, SRXCLK Low Time STXCLK, SRXCLK High Time STXCLK Low to SSIOTX Delay SSIORX to SRXCLK High Setup Time SSIORX from SRXCLK Hold Time 0 3CLK2 7CLK2/2 7CLK2/2 3CLK2 0 3CLK2 CLK2/8 CLK2/8 7CLK2/2 7CLK2/2 3CLK2 (2) CLK2/8 (Unit is MHz) CLK2/8 (Unit is MHz) (2) (2)
NOTE: 1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 4 of 5)
33 MHz Symbol Parameter Min. (ns) Max. (ns) 25 MHz Min. (ns) Max. (ns) Test Condition
Timer Control Unit (TCU) Inputs t107 t108 t109 t110 t111 t112 t112a TMRCLKn Frequency TMRCLKn Low TMRCLKn High TMRGATEn High Width TMRGATEn Low Width TMRGATEn to TMRCLK Setup Time (external TMRCLK only) TMRGATEn to TMRCLK Hold Time (external TMRCLK only) 60 60 50 50 10 11 8 60 60 50 50 10 11 8 (Unit is MHz)
Timer Control Unit (TCU) Outputs t113 t114 TMRGATEn Low to TMROUT Valid TMRCLKn Low to TMROUT Valid 29 29 32 32
Interrupt Control Unit (ICU) Inputs t115 t116 D7:0 Setup Time (INTA# Cycle 2) D7:0 Hold Time (INTA# Cycle 2) 7 4 7 4
Interrupt Control Unit (ICU) Outputs t117 CLK2 High to CAS2:0 Valid 25 28
DMA Unit Inputs t118 t119 t120 t121 DREQ Setup Time (Sync Mode) DREQ Hold Time (Sync Mode) DREQ Setup Time (Async Mode) DREQ Hold Time (Async Mode) 15 4 9 9 15 4 9 9 (2) (2)
NOTE: 1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
Datasheet
35
Intel386TM EX Embedded Microprocessor
Table 11. 5-Volt AC Characteristics (Sheet 5 of 5)
33 MHz Symbol Parameter Min. (ns) 15 4 9 9 Max. (ns) 25 MHz Min. (ns) 15 4 9 9 Max. (ns) Test Condition
t122 t123 t124 t125
EOP# Setup Time (Sync Mode) EOP# Hold Time (Sync Mode) EOP# Setup Time (Async Mode) EOP# Hold Time (Async Mode)
DMA Unit Outputs t126 t127 t128 t129 DACK# Output Valid Delay EOP# Active Delay EOP# Float Delay 4 4 4 21 25 25 4 4 4 25 25 25 (3)
JTAG Test-logic Unit TCK Frequency 10 10 (Unit is MHz)
NOTE: 1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 1 of 5)
25 MHz 3.0 V to 3.6 V Symbol Parameter Min. (ns) Operating Frequency t1 t2a t2b t3a t3b t4 t5 t6 t7 t8 t8a t9 t10 t10a t10b CLK2 Period CLK2 High Time CLK2 High Time CLK2 Low Time CLK2 Low Time CLK2 Fall Time CLK2 Rise Time A25:1 Valid Delay A25:1 Float Delay BHE#, BLE#, LOCK# Valid Delay SMIACT# Valid Delay BHE#, BLE#, LOCK# Float Delay M/IO#, D/C#, W/R#, ADS#, REFRESH# Valid Delay RD#, WR# Valid Delay WR# Valid Delay for the rising edge with respect to phase two (external late READY#) M/IO#, D/C#, W/R#, REFRESH#, ADS# Float Delay D15:0 Write Data Valid Delay D15:0 Write Data Float delay HLDA Valid Delay NA# Setup Time NA# Hold Time 4 4 4 4 4 4 4 4 0 20 7 4 7 5 7 7 32 29 32 32 23 32 30 37 4 4 4 4 4 4 4 4 Max. (ns) 25 Min. (ns) 0 25 8 5 8 6 8 8 36 36 34 34 32 34 32 37 (6) (2) (2) (2) (2) (2) (2) CL = 50 pF (3) CL = 50 pF CL = 50 pF (3) CL = 50 pF Max. (ns) 20 one-half CLK2 frequency in MHz(1) 20 MHz 2.7 V to 3.6 V Test Condition
t11 t12 t13 t14 t15 t16
NOTE:
4 4 4 4 9 12
30 31 20 30
4 4 4 4 9 15
34 34 28 32
(3) CL = 50 pF (3) CL = 50 pF
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
Datasheet
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Intel386TM EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 2 of 5)
25 MHz 3.0 V to 3.6 V Symbol Parameter Min. (ns) t19 t19a t20 t21 t22 t23 t24 t25 t26 t27 t27a t28 t28a t29 t30 t31 t32 t33 t34 t35 t36 t41 t41a t42
NOTE:
20 MHz 2.7 V to 3.6 V Test Condition Min. (ns) 17 19 4 11 6 22 5 13 4 16 16 16 16 16 5 (4) (4) (4) (4) (4) (4) 42 42 40 42 18 29 CL = 30 pF CL = 30 pF CL = 30 pF Max. (ns)
Max. (ns)
READY# Setup Time BS8# Setup Time READY#, BS8# Hold Time D15:0 Read Setup Time D15:0 Read Hold Time HOLD Setup Time HOLD Hold Time RESET Setup Time RESET Hold Time NMI Setup Time SMI# Setup Time NMI Hold Time SMI# Hold Time PEREQ, ERROR#, BUSY# Setup Time PEREQ, ERROR#, BUSY# Hold Time READY# Valid Delay READY# Float Delay LBA# Valid Delay CS6:0#, UCS# Valid Delay CLKOUT Valid Delay PWRDOWN Valid Delay A25:1, BHE#, BLE# Valid to WR# Low UCS#, CS6:0# Valid to WR# Low A25:1, BHE#, BLE# Hold After WR# High
15 17 4 9 6 17 5 12 4 16 16 16 16 14 5 4 4 4 4 4 4 0 0 0 33 33 31 33 (34 in SMM) 14 26
4 4 4 4 4 4 0 0 0
(6)
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 3 of 5)
25 MHz 3.0 V to 3.6 V Symbol Parameter Min. (ns) t42a t42b t43 t44 t45 t46 t47 t47a t48 t49 t50 t51 t51a t52 UCS#, CS6:0# Hold after WR# High A25:1. BHE#, BLE# Hold After WR# High D15:0 Output Valid to WR# High D15:0 Output Hold After WR# High WR# High to D15:0 Float WR# Pulse Width A25:1, BHE#, BLE# Valid to D15:0 Valid UCS#, CS6:0# Valid to D15D0 Valid RD# Low to D15:0 Input Valid D15:0 Hold After RD# High RD# High to D15:0 Float A25:1, BHE#, BLE# Hold After RD# High UCS#, CS6:0# Hold after RD# High RD# Pulse Width 0 0 3CLK2 -13 0 CLK2 0 0 3CLK2 -15 2CLK2 -10 4CLK241 4CLK2 42 3CLK2 - 39 0 CLK2 (3) 0 10 2CLK2 - 10 CLK2 -10 CLK2 + 10 2CLK2 -10 4CLK2 - 45 4CLK2 - 53 3CLK2 - 43 Max. (ns) Min. (ns) 0 10 2CLK2 - 10 CLK2 -10 CLK2 +10 (3) (7) (5) (5) (5) (7, 8) (5) Max. (ns) 20 MHz 2.7 V to 3.6 V Test Condition
Synchronous Serial I/O (SSIO) Unit t100 t101 t102
NOTE:
STXCLK, SRXCLK Frequency (Master Mode) STXCLK, SRXCLK Frequency (Slave Mode) STXCLK, SRXCLK Low Time 7CLK2/ 2
CLK2/8 CLK2/8 7CLK2/ 2
CLK2/8 CLK2/8
(Unit is MHz) (Unit is MHz) (2)
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
Datasheet
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Intel386TM EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 4 of 5)
25 MHz 3.0 V to 3.6 V Symbol Parameter Min. (ns) t103 t104 t105 t106 STXCLK, SRXCLK High Time STXCLK Low to SSIOTX Delay SSIORX to SRXCLK High Setup Time SSIORX from SRXCLK Hold Time 0 3CLK2 7CLK2/ 2 3CLK2 0 3CLK2 Max. (ns) Min. (ns) 7CLK2/ 2 3CLK2 (2) Max. (ns) (2) 20 MHz 2.7 V to 3.6 V Test Condition
Timer Control Unit (TCU) Inputs t107 t108 t109 t110 t111 t112 t112a TMRCLKn Frequency TMRCLKn Low TMRCLKn High TMRGATEn High Width TMRGATEn Low Width TMRGATEn to TMRCLK Setup Time (external TMRCLK only) TMRGATEn to TMRCLK Hold Time (external TMRCLK only) 60 60 50 50 10 8 60 60 50 50 15 8 (Unit is MHz)
19
19
Timer Control Unit (TCU) Outputs t113 t114
NOTE:
TMRGATEn Low to TMROUT Valid TMRCLKn Low to TMROUT Valid
44 48
52 52
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
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Datasheet
Intel386TM EX Embedded Microprocessor
Table 12. 3-Volt AC Characteristics (Sheet 5 of 5)
25 MHz 3.0 V to 3.6 V Symbol Parameter Min. (ns) Interrupt Control Unit (ICU) Inputs t115 t116 D7:0 Setup Time (INTA# Cycle 2) D7:0 Hold Time (INTA# Cycle 2) 9 6 11 6 Max. (ns) Min. (ns) Max. (ns) 20 MHz 2.7 V to 3.6 V Test Condition
Interrupt Control Unit (ICU) Outputs t117 CLK2 High to CAS2:0 Valid 36 46
DMA Unit Inputs t118 t119 t120 t121 t122 t123 t124 t125 DREQ Setup Time (Sync Mode) DREQ Hold Time (Sync Mode) DREQ Setup Time (Async Mode) DREQ Hold Time (Async Mode) EOP# Setup Time (Sync Mode) EOP# Hold Time (Sync Mode) EOP# Setup Time (Async Mode) EOP# Hold Time (Async Mode) 19 4 11 11 17 4 11 11 21 4 11 11 21 4 11 11 (2) (2)
DMA Unit Outputs t126 t127 t128 t129
NOTE:
DACK# Output Valid Delay EOP# Active Delay EOP# Float Delay
4 4 4
31 27 27
4 4 4
33 33 33 (3)
JTAG Test-logic Unit TCK Frequency 10 10 (Unit is MHz)
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. These are not tested. They are guaranteed by characterization. 3. Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested. 4. These inputs may be asynchronous to CLK2. The setup and hold specifications are given to ensure recognition within a specific CLK2 period. 5. These specifications are for information only and are not tested. They are intended to assist the designer in selecting memory speeds. For each wait state in the design add two CLK2 cycles to the specification. 6. This specification assumes that READY# goes active after the rising edge of phase 2, so that WR# goes inactive as a result of READY# falling. 7. This specification assumes that READY# goes active before the rising edge of phase 2, so that WR# goes inactive as a result of phase 2 rising. 8. This specification applies if READY# is generated internally.
Datasheet
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Intel386TM EX Embedded Microprocessor
Figure 10. AC Test Loads
CPU Output CL
Figure 11. CLK2 Waveform
t1 t2a t2b CLK2 A B C t5 t4
t3b t3a
A = Vcc - 0.8 for Vcc = 4.5 - 5.5, Vcc - 0.6 for Vcc = 2.7 - 3.6 B = Vcc/2 C = 0.8V
42
Datasheet
Intel386TM EX Embedded Microprocessor
Figure 12. AC Timing Waveforms -- Input Setup and Hold Timing
TX CLK2 t19a, t118, t120 t122, t124 t19 t119, t121 t123, t125 t20 PH2 PH1 TX PH2 PH1 TX
READY# (Input) BS8# DREQ EOP# (Input)
t23 HOLD t115 t21 D15:0 (Input) t29 BUSY# ERROR# PEREQ
t24
t116 t22
t30
t15 NA# t27a t27 NMI SMI#
t16
t28a t28
A2736-01
Datasheet
43
Intel386TM EX Embedded Microprocessor
Figure 13. AC Timing Waveforms -- Output Valid Delay Timing
TX
CLK2
PH2
PH1
TX
PH2
PH1
TX
t8, t8a
BHE#, BLE# LOCK#, SMIACT#
Min
Max Valid n+1
Valid n t10, t31, t33 t126, t127 Min Valid n t10a, t6, t34 Min Valid n t117, t10a, t12 Min
W/R#, M/IO#, D/C# ADS#,REFRESH# LBA#, DACK# EOP# (Output) READY# (Output) A25:1, CS6:0#,UCS#, RD# Inactive D15:0, CAS2:0 RD#, WR# Active, WR# Inactive (early READY#)
Max Valid n+1
Max Valid n+1 Max Valid n+1
Valid n
HLDA
A2737-01
Figure 14. AC Timing Waveforms -- Output Valid Delay Timing for External Late READY#
T1
CLK2
T2
T1
ADS#
External READY# t10b WR#
A4398-01
44
Datasheet
Intel386TM EX Embedded Microprocessor
Figure 15. AC Timing Waveforms -- Output Float Delay and HLDA Valid Delay Timing
Th PH2
CLK2
TI or T1 PH2 PH1 PH2
PH1
t8 t9
BHE#, BLE# LOCK#
Min
Max (High Z)
Min
Max
t32, t11
W/R#, M/IO# D/C#, ADS# REFRESH# READY# (Output) A25:1
Min
Max
t10 (High Z)
Min
Max
t7
Min
Max
t6 (High Z)
Min
Max
t13
D15:0
Min
Max
t12 (High Z)
Min
Max
t13 Also applies to data float when write cycle is followed by read or idle. t14
HLDA
A2738-01
Min
Max
t14
Min
Max
Figure 16. AC Timing Waveforms -- RESET Setup and Hold Timing and Internal Phase
Reset PH2 or PH1 CLK2 t26 RESET t25 PH2 or PH1
Initialization Sequence PH2 PH1
Datasheet
45
Intel386TM EX Embedded Microprocessor
Figure 17. AC Timing Waveforms -- Relative Signal Timing
T1 CLK2 T2 Ti
PH2
A25:1, BLE#, BHE# UCS#, CS6:0# t41a WR# t41 t46 t42 t42a
D15:0 (Out)
t43 t51
t44 t45
RD# t48 t47 D15:0 (In) t47a
t52
t51a
t50
t49
A2705-01
Figure 18. AC Timing Waveforms -- SSIO Timing
t100, t101 t102 STXCLK t104 SSIOTX
Valid TX Data
t103
t100, t101 t102 SRXCLK t105 SSIORX t106
A2712-01
t103
Valid RX Data
Figure 19. AC Timing Waveforms -- Timer/Counter Timing
t107 t109 TMRCLK t112 TMRGATE t113 TMROUT t114 t112a t111 t110 t108
46
Datasheet
Intel386TM EX Embedded Microprocessor
7.0
Bus Cycle Waveforms
Figures 20 through 30 present various bus cycles that are generated by the processor. What is shown in the figure is the relationship of the various bus signals to CLK2. These figures along with the information present in AC Specifications allow the user to determine critical timing analysis for a given application.
Figure 20. Basic Internal and External Bus Cycles
Idle Cycle 1 Cycle Nonpipelined External (Write) [Late Ready] Cycle 2 Nonpipelined Internal (Read) Idle Cycle 3 Nonpipelined Cycle Internal (Write) [Early Ready] Idle Cycle 4 Nonpipelined Cycle External (Read)
State CLK2 CLKOUT A25:1, BHE# BLE#, D/C# M/IO# REFRESH# W/R# WR# RD# ADS# NA#
Ti
T1
T2
T1
T2
T1
T2
Ti
T1
T2
Ti
Valid 1
Valid 2
Valid 3
Valid 4
READY#
End Cycle 1
End Cycle 2
End Cycle 3
End Cycle 4
LBA# BS8# LOCK# D15:0
Valid 1 Out 1 Valid 2 In 2 Valid 3 Valid 4 In 4
A2486-03
Out 3
Datasheet
47
Intel386TM EX Embedded Microprocessor
Figure 21. Nonpipelined Address Read Cycles
Idle Cycle 1 Non-pipelined External (Read) T1 T2 Cycle 2 Non-pipelined External (Read) T1 T2 T2 Idle
Ti CLK2
Ti
CLKOUT BHE#, BLE#, A25:1 M/IO#, D/C# REFRESH# W/R# Valid1 Valid2
WR#
RD# ADS#
NA# READY#
End Cycle LBA# BS8# LOCK# Valid1 Valid2 In1
End Cycle
D15:0
In2
A2487-03
48
Datasheet
Intel386TM EX Embedded Microprocessor
Figure 22. Pipelined Address Cycle
Cycle 1 Pipelined (Write) [Late Ready] T1P T2P T2P CLK2 CLKOUT BHE#, BLE#, A25:1, M/IO#, D/C# Valid1 Valid2 Cycle 2 Non-pipelined (Read) T1P T2 T2P Cycle 3 Pipelined (Write) [Late Ready] T1P T2i T2P Cycle 4 Pipelined (Read) T1P T2
Valid3
Valid4
ADS# is asserted as soon as the CPU has another bus cycle to perform, which is not always immediately after NA# is asserted. W/R# WR# RD#
ADS# Note ADS# is asserted in every T2P state. NA# Asserting NA# more than once during any cycle has no additional effects READY# NA# could have been asserted in T1P if desired. Assertion now is the latest time possible to allow the CPU to enter T2P state to maintain pipelining in cycle 3. As long as the CPU enters the T2P state during Cycle 3, address pipelining is maintained in Cycle 4.
LBA# BS8# LOCK# Valid 1 Valid 2 In 2 Valid 3 Out 3
A2477-03
Valid 4
D15:0
Out
Out 1
Datasheet
49
Intel386TM EX Embedded Microprocessor
Figure 23. 16-bit Cycles to 8-bit Devices (using BS8#)
Low Byte Write
[Late Ready]
High Byte Write
[Late Ready]
Low Byte Read T1 T2
High Byte Read T1 T2
Idle Cycles Ti Ti
State
CLK2 CLKOUT
T1
T2
T1
T2
A25:1 M/IO# D/C# BLE# BHE# W/R# WR# RD# ADS# NA#
Valid 1
Valid 2
Must be high READY# BS8# LOCK# D15:8 D7:0 Valid 1 Data Out High Data Out Low Data Out High Data In Low Data In High
A3375-01
Valid 2
50
Datasheet
Intel386TM EX Embedded Microprocessor
Figure 24. Basic External Bus Cycles
Cycle 1 Nonpipelined External (Write) [Late Ready] Cycle 2 Nonpipelined External (Read) Cycle 3 Idle Cycle Nonpipelined External (Write) [Late Ready] Cycle 4 Nonpipelined External (Read)
State CLK2 CLKOUT A25:1, BHE# BLE#, D/C# M/IO# REFRESH# W/R# WR# RD# ADS# NA# READY# LBA# BS8# LOCK# D15:0
T1
T2
T1
T2
Ti
T1
T2
T1
T2
Valid 1
Valid 2
Valid 3
Valid 4
Valid 1 Out 1
Valid 2 In 2
Valid 3 Out 3
Valid 4 In 4
A2305-02
Datasheet
51
Intel386TM EX Embedded Microprocessor
Figure 25. Nonpipelined Address Write Cycles
Idle Cycle 1 Nonpipelined External (Write) [Late Ready] T1 T2 Cycle 2 Nonpipelined External (Write) [Early Ready] T1 T2 T2 Idle
Ti CLK2 CLKOUT BHE#, BLE#, A25:1 M/IO#, D/C# REFRESH# W/R# WR#
Ti
Valid1
Valid2
RD# ADS#
NA# READY#
End Cycle 1 LBA#
End Cycle 2
BS8# Valid 2
LOCK#
Valid 1 Out 1
D15:0
Out 2
A2488-02
52
Datasheet
Intel386TM EX Embedded Microprocessor
Figure 26. Halt Cycle
Cycle 1 Nonpipelined (Write) [Late Ready] T1 CLK2 CLKOUT CPU remains halted until INTR, SMI#, NMI, or RESET is asserted. CPU responds to HOLD input while in the HALT state. T2 Cycle 2 Nonpipelined (Halt) T1 T2 Idle
Ti
Ti
Ti
Ti
BHE#, A1, M/IO#, W/R#
Valid 1 Valid 1
A25:2, BLE#, D/C#
WR# RD# ADS#
NA# READY# LBA#
LOCK# D15:0
Valid 1 Out
Valid 2 Undefined Float
HALT cycle must be acknowledged by READY# asserted. This READY# could be generated internally or externally.
A2492-02
Datasheet
53
Intel386TM EX Embedded Microprocessor
Figure 27. Basic Refresh Cycle
Idle Cycle 1 Nonpipelined External (Read) T1 T2 Idle Cycle 2 Refresh Idle Cycle 3 Nonpipelined External (Write) [Late Ready] Ti T1 T2
Ti CLK2 CLKOUT UCS#, CS6:0#, BHE#, BLE# M/IO#, D/C# A25:1
Ti
T1
T2
T2
Ti
Valid 1
Valid 3 Valid 2
Valid 1
Valid 3
REFRESH# W/R#
WR# RD# ADS#
NA#
READY# LBA# Valid 1 Float Valid 2
LOCK# D15:0
In
Out
HOLD
HLDA
A2491-02
54
Datasheet
Intel386TM EX Embedded Microprocessor
Figure 28. Refresh Cycle During HOLD/HLDA
Idle HOLD Acknowledge Th Th Th Idle Cycle 1 Refresh T1 T2 Ti Idle HOLD Acknowledge Ti Th Th
Ti CLK2 CLKOUT BHE#, BLE# M/IO#, D/C# REFRESH#
Ti
Floating
Floating
A25:1
Floating
Valid 1
Floating
W/R#
Floating
Floating
WR# RD# Floating ADS# Floating
NA# Floating READY# Floating
LBA# Floating Floating D15:0 Floating
LOCK#
HOLD HLDA Due to refresh pending.
A2493-02
Datasheet
55
Intel386TM EX Embedded Microprocessor
Figure 29. LOCK# Signal During Address Pipelining
Unlocked Bus Cycle CLKOUT Address Asserted BLE#, BHE#, A25:1 Locked Bus Cycle Locked Bus Cycle Unlocked Bus Cycle
LOCK Deasserted LOCK#
READY#
A2489-02
Figure 30. Interrupt Acknowledge Cycles
Previous Interrupt Cycle Acknowledge Cycle 1 (Internal) T2 T1 T2 CLK2 CLKOUT Idle (Four bus states) Ti Ti Ti Ti Interrupt Acknowledge Cycle 2 (Internal) T1 T2 Idle
Ti
Ti
BHE# BLE#, A25:19, CAS2:0,A15:3, A1 M/IO#, D/C#, W/R# A2
WR# RD#
ADS#
READY# LBA#
LOCK#
A2490-03
56
Datasheet
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